The transformation of semi-conductor wafer disks into integrated circuit chips often involves many steps where the disks are repeatedly processed, stored and transported. The wafers must be transported from workstation to workstation and from facility to facility. Wafer disks are brittle and are easily damaged by physical shock. Also, build-up and discharge of static charges in the vicinity of semiconductor wafers can be catastrophic. Due to the delicate nature of the wafers and their extreme value, it is vital that they are properly protected throughout these procedures from contaminates, and physical and electrical damage.
Specialized carriers or containers are used for handling, storing, and shipping wafers. Such devices normally hold the wafers in axially aligned arrays with, for example, twenty-five wafers in an array. A principal component of the containers is a means for supporting the wafers during handling to protect against physical damage from shock and vibration. This wafer support means may be provided with a path to ground for static dissipation through a machine interface on the bottom of the container.
The prior art containers typically have wafer restraint structures on the door of the container that cooperate with the wafer supports in the container when the door is in place. These wafer restraint structures function to cushion the wafers and restrain their movement to prevent damage from shock. Prior wafer restraint structures, however, have not been quite satisfactory in some cases. In some cases, the wafer restraint structures may enable the wafer to translate too far vertically during physical shock events, causing damage to the wafer itself or to adjacent wafers. In some cases, the wafer may even be dislodged from the wafer restraints. In other cases, wafers may become cross-slotted between adjacent wafer restraints during such physical shock events.
What is needed in the industry is an improved wafer restraint system for a wafer carrier that alleviates the aforementioned problems by providing improved wafer restraint during physical shock events.